Unlocking the CPU: 16 Essential Resources for Assembly and Machine Code
dev.to·1d·
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🔧RISC-V Assembler
My first experience with Formal Methods | ZipCPU
zipcpu.com·3d
🔧Hardware Verification
Program Synthesis is Interesting and Open
stephendiehl.com·10h·
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💻Programming languages
Adding linear-time lookbehinds to RE2
systemf.epfl.ch·12h·
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🔍RegEx Engines
DSA Fundamentals #1: A Practical Guide to Propositional Logic
beyondit.blog·2d
🧮Theorem Proving
Basic facts about GPUs
damek.github.io·5h·
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🖥️Hardware Architecture
bytecodealliance/wasm-micro-runtime
github.com·1d
⚙️WASM Runtime
Coping with Complexity
slott56.github.io·23h
🔗Concatenative Programming
How to Compile a Large Language Model (LLM) to RISC-V
siliscale.com·18h·
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🧩RISC-V Assembly
To Bind and Loose a Reference
thephd.dev·11h·
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🎯Gradual Typing
Lockfree Programming: A Mental Model
xorvoid.com·1d·
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⚡Hardware Transactional Memory
Transitioning from Assembly to C: Challenges and Solutions for Programmers Effectively
dev.to·6h·
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🔩Systems Programming
The Architecture of Web-Based Graphic Editors and 7 Design Patterns (Part 2)
dev.to·42m·
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✨Effect Handlers
Microcontrollers: Getting Started
youtube.com·1d
🔌Microcontrollers
The FPGA Turns 40!
adiuvoengineering.com·1d·
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🔍FPGA Verification
Revolutionizing Edge AI: Deploying Models with WebAssembly and WASI-NN
dev.to·5h·
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🌐WASI
Language Workbenches: The Killer-App for Domain Specific Languages? (2005)
martinfowler.com·18h·
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🗣️Domain-Specific Languages
Setting New Standards in FPGA Timing Constraint Excellence by Ujjwal Singh
hackernoon.com·2d
🔧Hardware Verification
Reflection and open implementations (2006)
dcc.uchile.cl·20h·
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🌐Protocol Synthesis
[D] RL/GRPO for lossless compression of text passages into 'least token representation', then using this emergent 'language' as the basis for reasoning instead ...
reddit.com·13h·
Discuss: r/MachineLearning
🧠Learned Compression