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CPU Microarchitecture
⚡ CPU Microarchitecture
Pipeline Design, Branch Prediction, Cache Hierarchy, Superscalar
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The Tick-Tock AI Development Cycle.
🖥️
Hardware Architecture
wilsoniumite.com
·
5h
5 hours ago
Actions for The Tick-Tock AI Development Cycle.
uiCA: Accurate Throughput
Prediction
of Basic Blocks on Recent Intel
Microarchitectures
🖥️
Hardware Architecture
Content type:
Academic
arxiv.org
·
22h
22 hours ago
·
Hacker News
Actions for uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
How much do amd64
microarchitecture
levels
help in Go?
🖥️
Modern CPU
Content type:
Blog
lemire.me
·
4d
4 days ago
·
Lobsters
,
Hacker News
,
r/golang
Actions for How much do amd64 microarchitecture levels help in Go?
Intel 8086, the First x86 chip, Enters its 50th Year in 2027
🖥️
Hardware Architecture
techpowerup.com
·
1d
1 day ago
Actions for Intel 8086, the First x86 chip, Enters its 50th Year in 2027
Why x86 Zeroes a
Register
With `xor eax, eax`
🔢
Bitwise Algorithms
Content type:
Blog
debasishg.github.io
·
2d
2 days ago
Actions for Why x86 Zeroes a Register With `xor eax, eax`
Apple Chip
Architecture
from 1977 to 2026
🧲
RISC-V Archaeology
Content type:
News
Content type:
Blog
blog.jacobstechtavern.com
·
1d
1 day ago
Actions for Apple Chip Architecture from 1977 to 2026
Advanced Vector Extensions 512 Acceleration of LSH and LEA-GCM
⚡
SIMD Optimization
eprint.iacr.org
·
6d
6 days ago
Actions for Advanced Vector Extensions 512 Acceleration of LSH and LEA-GCM
Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
⚡
Parallel Computing
openjdk.org
·
1d
1 day ago
·
r/java
Actions for Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
Founding Engineer - FPGA, RTL, & ASIC
Architect
at Zettascale
⚙️
Logic Synthesis
ycombinator.com
·
6d
6 days ago
·
Hacker News
Actions for Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale
The copy_if Speedup That Wasn't About copy_if, Or AVX-512
🖥️
Modern CPU
hftuniversity.com
·
6d
6 days ago
·
Substack
Actions for The copy_if Speedup That Wasn't About copy_if, Or AVX-512
Sequential hardness of a MUL-XOR-shift permutation: open questions
⚙️
Logic Synthesis
Content type:
Code
github.com
·
1d
1 day ago
·
r/crypto
Actions for Sequential hardness of a MUL-XOR-shift permutation: open questions
Fractal OS Lets Security Researchers See What Their CPUs Really Do
🔓
Open Source Software
Content type:
News
spectrum.ieee.org
·
1d
1 day ago
Actions for Fractal OS Lets Security Researchers See What Their CPUs Really Do
The last bit –
Part
3
⚙️
Modern Assembly
thinkingeek.com
·
4d
4 days ago
Actions for The last bit – Part 3
Aging
Mice
Became Stronger When Scientists Boosted One Protein
🖥️
Hardware Architecture
sciencealert.com
·
5d
5 days ago
Actions for Aging Mice Became Stronger When Scientists Boosted One Protein
Intel's mysterious new datacenter GPU is what Nvidia's Rubin CPX nearly was
🖥️
Hardware Architecture
theregister.com
·
6d
6 days ago
Actions for Intel's mysterious new datacenter GPU is what Nvidia's Rubin CPX nearly was
AMD Ryzen 9 9950X3D2 Dual Edition Review - Maximum
Cache
🖥️
Hardware Architecture
techpowerup.com
·
1d
1 day ago
·
r/hardware
Actions for AMD Ryzen 9 9950X3D2 Dual Edition Review - Maximum Cache
Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput
⚡
Parallel Computing
Content type:
Blog
elastic.co
·
5d
5 days ago
Actions for Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput
Spectre and Meltdown: When CPUs Leak Secrets by Guessing
🔌
Operating system internals
Content type:
Blog
havenmessenger.com
·
5d
5 days ago
·
DEV
Actions for Spectre and Meltdown: When CPUs Leak Secrets by Guessing
What Arm-based innovations happened in May 2026?
⚡
Performance Tools
Content type:
Blog
newsroom.arm.com
·
5d
5 days ago
Actions for What Arm-based innovations happened in May 2026?
MOSAIC: A Workload-Driven Simulation and
Design-Space
Exploration Framework for Heterogeneous NPUs
📊
Frequency Analysis
Content type:
Academic
arxiv.org
·
5d
5 days ago
Actions for MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
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